As electronic devices become increasingly complex, device designers have been required to take internal delays of device components into consideration. In digital circuits, these internal delays contribute to the phenomenon known as clock skew, in which a clock or other reference signal that is input into a digital circuit is perceived by different components of the digital circuit as arriving at different times. That is, as the clock signal propagates throughout the digital circuit, components that expect to receive the same clock signal may actually receive clock signals that are out of phase with each other. In synchronous digital circuits, proper timing between components is required for driving the digital logic of the circuits and initiating events such as latching of data, driving data, changing logic states, shifting pointers, etc. Thus, the internal delays may cause the components to become unsynchronized, resulting in internal signals that occur at unanticipated times, often with harmful results such as device malfunction or failure.
There are two common methods for eliminating clock skew: PLL (Phase Locked Loop) and DLL (Delay Locked Loop). A PLL uses an adjustable oscillator to reproduce the frequency and phase of a reference clock. A DLL uses an array of fixed delay elements to add to the (skewed) source clock so that it matches the (unskewed) reference clock.